335 lines
10 KiB
C++
Executable file
335 lines
10 KiB
C++
Executable file
/* Audio Library for Teensy 3.X
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* Copyright (c) 2017, Paul Stoffregen, paul@pjrc.com
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*
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* Development of this audio library was funded by PJRC.COM, LLC by sales of
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* Teensy and Audio Adaptor boards. Please support PJRC's efforts to develop
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* open source software by purchasing Teensy or other PJRC products.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice, development funding notice, and this permission
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* notice shall be included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <Arduino.h>
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#include "output_tdm.h"
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#include "memcpy_audio.h"
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#include "utility/imxrt_hw.h"
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audio_block_t * AudioOutputTDM::block_input[16] = {
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nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr,
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nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr
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};
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bool AudioOutputTDM::update_responsibility = false;
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DMAChannel AudioOutputTDM::dma(false);
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DMAMEM __attribute__((aligned(32)))
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static uint32_t zeros[AUDIO_BLOCK_SAMPLES/2];
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DMAMEM __attribute__((aligned(32)))
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static uint32_t tdm_tx_buffer[AUDIO_BLOCK_SAMPLES*16];
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void AudioOutputTDM::begin(void)
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{
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dma.begin(true); // Allocate the DMA channel first
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for (int i=0; i < 16; i++) {
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block_input[i] = nullptr;
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}
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// TODO: should we set & clear the I2S_TCSR_SR bit here?
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config_tdm();
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#if defined(KINETISK)
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CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0
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dma.TCD->SADDR = tdm_tx_buffer;
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dma.TCD->SOFF = 4;
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dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(2) | DMA_TCD_ATTR_DSIZE(2);
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dma.TCD->NBYTES_MLNO = 4;
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dma.TCD->SLAST = -sizeof(tdm_tx_buffer);
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dma.TCD->DADDR = &I2S0_TDR0;
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dma.TCD->DOFF = 0;
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dma.TCD->CITER_ELINKNO = sizeof(tdm_tx_buffer) / 4;
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dma.TCD->DLASTSGA = 0;
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dma.TCD->BITER_ELINKNO = sizeof(tdm_tx_buffer) / 4;
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dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
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dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX);
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update_responsibility = update_setup();
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dma.enable();
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I2S0_TCSR = I2S_TCSR_SR;
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I2S0_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;
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#elif defined(__IMXRT1062__)
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CORE_PIN7_CONFIG = 3; //1:TX_DATA0
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dma.TCD->SADDR = tdm_tx_buffer;
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dma.TCD->SOFF = 4;
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dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(2) | DMA_TCD_ATTR_DSIZE(2);
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dma.TCD->NBYTES_MLNO = 4;
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dma.TCD->SLAST = -sizeof(tdm_tx_buffer);
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dma.TCD->DADDR = &I2S1_TDR0;
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dma.TCD->DOFF = 0;
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dma.TCD->CITER_ELINKNO = sizeof(tdm_tx_buffer) / 4;
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dma.TCD->DLASTSGA = 0;
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dma.TCD->BITER_ELINKNO = sizeof(tdm_tx_buffer) / 4;
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dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
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dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_TX);
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update_responsibility = update_setup();
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dma.enable();
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I2S1_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE;
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I2S1_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;
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#endif
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dma.attachInterrupt(isr);
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}
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// TODO: needs optimization...
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static void memcpy_tdm_tx(uint32_t *dest, const uint32_t *src1, const uint32_t *src2)
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{
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uint32_t i, in1, in2, out1, out2;
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for (i=0; i < AUDIO_BLOCK_SAMPLES/4; i++) {
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in1 = *src1++;
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in2 = *src2++;
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out1 = (in1 << 16) | (in2 & 0xFFFF);
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out2 = (in1 & 0xFFFF0000) | (in2 >> 16);
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*dest = out1;
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*(dest + 8) = out2;
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in1 = *src1++;
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in2 = *src2++;
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out1 = (in1 << 16) | (in2 & 0xFFFF);
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out2 = (in1 & 0xFFFF0000) | (in2 >> 16);
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*(dest + 16)= out1;
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*(dest + 24) = out2;
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dest += 32;
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}
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}
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void AudioOutputTDM::isr(void)
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{
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uint32_t *dest;
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const uint32_t *src1, *src2;
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uint32_t i, saddr;
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saddr = (uint32_t)(dma.TCD->SADDR);
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dma.clearInterrupt();
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if (saddr < (uint32_t)tdm_tx_buffer + sizeof(tdm_tx_buffer) / 2) {
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// DMA is transmitting the first half of the buffer
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// so we must fill the second half
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dest = tdm_tx_buffer + AUDIO_BLOCK_SAMPLES*8;
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} else {
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// DMA is transmitting the second half of the buffer
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// so we must fill the first half
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dest = tdm_tx_buffer;
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}
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if (update_responsibility) AudioStream::update_all();
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#if IMXRT_CACHE_ENABLED >= 2
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uint32_t *dc = dest;
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#endif
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for (i=0; i < 16; i += 2) {
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src1 = block_input[i] ? (uint32_t *)(block_input[i]->data) : zeros;
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src2 = block_input[i+1] ? (uint32_t *)(block_input[i+1]->data) : zeros;
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memcpy_tdm_tx(dest, src1, src2);
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dest++;
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}
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#if IMXRT_CACHE_ENABLED >= 2
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arm_dcache_flush_delete(dc, sizeof(tdm_tx_buffer) / 2 );
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#endif
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for (i=0; i < 16; i++) {
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if (block_input[i]) {
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release(block_input[i]);
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block_input[i] = nullptr;
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}
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}
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}
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void AudioOutputTDM::update(void)
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{
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audio_block_t *prev[16];
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unsigned int i;
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__disable_irq();
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for (i=0; i < 16; i++) {
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prev[i] = block_input[i];
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block_input[i] = receiveReadOnly(i);
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}
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__enable_irq();
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for (i=0; i < 16; i++) {
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if (prev[i]) release(prev[i]);
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}
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}
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#if defined(KINETISK)
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// MCLK needs to be 48e6 / 1088 * 512 = 22.588235 MHz -> 44.117647 kHz sample rate
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//
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#if F_CPU == 96000000 || F_CPU == 48000000 || F_CPU == 24000000
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// PLL is at 96 MHz in these modes
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#define MCLK_MULT 4
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#define MCLK_DIV 17
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#elif F_CPU == 72000000
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#define MCLK_MULT 16
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#define MCLK_DIV 51
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#elif F_CPU == 120000000
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#define MCLK_MULT 16
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#define MCLK_DIV 85
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#elif F_CPU == 144000000
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#define MCLK_MULT 8
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#define MCLK_DIV 51
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#elif F_CPU == 168000000
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#define MCLK_MULT 16
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#define MCLK_DIV 119
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#elif F_CPU == 180000000
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#define MCLK_MULT 32
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#define MCLK_DIV 255
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#define MCLK_SRC 0
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#elif F_CPU == 192000000
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#define MCLK_MULT 2
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#define MCLK_DIV 17
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#elif F_CPU == 216000000
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#define MCLK_MULT 12
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#define MCLK_DIV 17
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#define MCLK_SRC 1
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#elif F_CPU == 240000000
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#define MCLK_MULT 2
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#define MCLK_DIV 85
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#define MCLK_SRC 0
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#elif F_CPU == 256000000
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#define MCLK_MULT 12
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#define MCLK_DIV 17
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#define MCLK_SRC 1
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#else
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#error "This CPU Clock Speed is not supported by the Audio library";
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#endif
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#ifndef MCLK_SRC
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#if F_CPU >= 20000000
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#define MCLK_SRC 3 // the PLL
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#else
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#define MCLK_SRC 0 // system clock
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#endif
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#endif
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#endif
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void AudioOutputTDM::config_tdm(void)
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{
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#if defined(KINETISK)
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SIM_SCGC6 |= SIM_SCGC6_I2S;
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SIM_SCGC7 |= SIM_SCGC7_DMA;
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SIM_SCGC6 |= SIM_SCGC6_DMAMUX;
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// if either transmitter or receiver is enabled, do nothing
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if (I2S0_TCSR & I2S_TCSR_TE) return;
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if (I2S0_RCSR & I2S_RCSR_RE) return;
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// enable MCLK output
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I2S0_MCR = I2S_MCR_MICS(MCLK_SRC) | I2S_MCR_MOE;
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while (I2S0_MCR & I2S_MCR_DUF) ;
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I2S0_MDR = I2S_MDR_FRACT((MCLK_MULT-1)) | I2S_MDR_DIVIDE((MCLK_DIV-1));
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// configure transmitter
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I2S0_TMR = 0;
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I2S0_TCR1 = I2S_TCR1_TFW(4);
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I2S0_TCR2 = I2S_TCR2_SYNC(0) | I2S_TCR2_BCP | I2S_TCR2_MSEL(1)
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| I2S_TCR2_BCD | I2S_TCR2_DIV(0);
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I2S0_TCR3 = I2S_TCR3_TCE;
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I2S0_TCR4 = I2S_TCR4_FRSZ(7) | I2S_TCR4_SYWD(0) | I2S_TCR4_MF
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| I2S_TCR4_FSE | I2S_TCR4_FSD;
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I2S0_TCR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31);
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// configure receiver (sync'd to transmitter clocks)
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I2S0_RMR = 0;
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I2S0_RCR1 = I2S_RCR1_RFW(4);
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I2S0_RCR2 = I2S_RCR2_SYNC(1) | I2S_TCR2_BCP | I2S_RCR2_MSEL(1)
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| I2S_RCR2_BCD | I2S_RCR2_DIV(0);
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I2S0_RCR3 = I2S_RCR3_RCE;
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I2S0_RCR4 = I2S_RCR4_FRSZ(7) | I2S_RCR4_SYWD(0) | I2S_RCR4_MF
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| I2S_RCR4_FSE | I2S_RCR4_FSD;
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I2S0_RCR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31);
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// configure pin mux for 3 clock signals
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CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK) - 44.1kHz
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CORE_PIN9_CONFIG = PORT_PCR_MUX(6); // pin 9, PTC3, I2S0_TX_BCLK - 11.2 MHz
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CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK - 22.5 MHz
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#elif defined(__IMXRT1062__)
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CCM_CCGR5 |= CCM_CCGR5_SAI1(CCM_CCGR_ON);
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// if either transmitter or receiver is enabled, do nothing
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if (I2S1_TCSR & I2S_TCSR_TE) return;
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if (I2S1_RCSR & I2S_RCSR_RE) return;
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//PLL:
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int fs = AUDIO_SAMPLE_RATE_EXACT;
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// PLL between 27*24 = 648MHz und 54*24=1296MHz
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int n1 = 4; //SAI prescaler 4 => (n1*n2) = multiple of 4
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int n2 = 1 + (24000000 * 27) / (fs * 256 * n1);
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double C = ((double)fs * 256 * n1 * n2) / 24000000;
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int c0 = C;
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int c2 = 10000;
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int c1 = C * c2 - (c0 * c2);
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set_audioClock(c0, c1, c2);
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// clear SAI1_CLK register locations
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CCM_CSCMR1 = (CCM_CSCMR1 & ~(CCM_CSCMR1_SAI1_CLK_SEL_MASK))
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| CCM_CSCMR1_SAI1_CLK_SEL(2); // &0x03 // (0,1,2): PLL3PFD0, PLL5, PLL4
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n1 = n1 / 2; //Double Speed for TDM
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CCM_CS1CDR = (CCM_CS1CDR & ~(CCM_CS1CDR_SAI1_CLK_PRED_MASK | CCM_CS1CDR_SAI1_CLK_PODF_MASK))
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| CCM_CS1CDR_SAI1_CLK_PRED(n1-1) // &0x07
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| CCM_CS1CDR_SAI1_CLK_PODF(n2-1); // &0x3f
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IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK))
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| (IOMUXC_GPR_GPR1_SAI1_MCLK_DIR | IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(0)); //Select MCLK
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// configure transmitter
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int rsync = 0;
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int tsync = 1;
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I2S1_TMR = 0;
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I2S1_TCR1 = I2S_TCR1_RFW(4);
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I2S1_TCR2 = I2S_TCR2_SYNC(tsync) | I2S_TCR2_BCP | I2S_TCR2_MSEL(1)
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| I2S_TCR2_BCD | I2S_TCR2_DIV(0);
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I2S1_TCR3 = I2S_TCR3_TCE;
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I2S1_TCR4 = I2S_TCR4_FRSZ(7) | I2S_TCR4_SYWD(0) | I2S_TCR4_MF
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| I2S_TCR4_FSE | I2S_TCR4_FSD;
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I2S1_TCR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31);
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I2S1_RMR = 0;
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I2S1_RCR1 = I2S_RCR1_RFW(4);
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I2S1_RCR2 = I2S_RCR2_SYNC(rsync) | I2S_TCR2_BCP | I2S_RCR2_MSEL(1)
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| I2S_RCR2_BCD | I2S_RCR2_DIV(0);
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I2S1_RCR3 = I2S_RCR3_RCE;
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I2S1_RCR4 = I2S_RCR4_FRSZ(7) | I2S_RCR4_SYWD(0) | I2S_RCR4_MF
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| I2S_RCR4_FSE | I2S_RCR4_FSD;
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I2S1_RCR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31);
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CORE_PIN23_CONFIG = 3; //1:MCLK
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CORE_PIN21_CONFIG = 3; //1:RX_BCLK
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CORE_PIN20_CONFIG = 3; //1:RX_SYNC
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#endif
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}
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