Dooho Yi
91f92c0e6c
migration from 'smp_v1p0' dev. for 'sampler' -> skip irrelavant note msg. and keep playing
255 lines
8.2 KiB
C++
255 lines
8.2 KiB
C++
/*
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* HiFi Audio Codec Module support library for Teensy 3.x
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*
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* Copyright 2015, Michele Perla
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*
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*/
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#ifndef control_ak4558_h_
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#define control_ak4558_h_
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#include "AudioControl.h"
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#define AK4558_SERIAL_DEBUG 1
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//if 1, then Serial Monitor will show debug information about configuration of the AK4558
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// for Teensy audio lib operation the following settings are needed
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// 1fs = 44.1 KHz
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// sample size = 16 bits
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// MCKI : 11.2896 MHz
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// BICK : 1.4112 MHz
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// LRCK : 44.100 KHz
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// to do so we need to set the following bits:
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// PMPLL = 0 (EXT Slave Mode; disables internal PLL and uses ext. clock) (by DEFAULT)
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// ACKS = 0 (Manual Setting Mode; disables automatic clock selection) (by DEFAULT)
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// DFS1-0 = 00 (Sampling Speed = Normal Speed Mode, default)
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// MCKS1-0 = 00 (Master Clock Input Frequency Select, set 256fs for Normal Speed Mode -> 11.2896 MHz)
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// BCKO1-0 = 00 (BICK Output Frequency at Master Mode = 32fs = 1.4112 MHz)
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// TDM1-0 = 00 (Time Division Multiplexing mode OFF) (by DEFAULT)
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// DIF2-1-0 = 011 ( 16 bit I2S compatible when BICK = 32fs)
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#ifndef PIN_PDN
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#define PIN_PDN 1
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#endif
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// Power-Down & Reset Mode Pin
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// “L”: Power-down and Reset, “H”: Normal operation
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// The AK4558 should be reset once by bringing PDN pin = “L”
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#ifndef AK4558_CAD1
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#define AK4558_CAD1 1
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#endif
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// Chip Address 1 pin
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// set to 'H' by default, configurable to 'L' via a jumper on bottom side of the board
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#ifndef AK4558_CAD0
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#define AK4558_CAD0 1
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#endif
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// Chip Address 0 pin
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// set to 'H' by default, configurable to 'L' via a jumper on bottom side of the board
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#define AK4558_I2C_ADDR (0x10 + (AK4558_CAD1<<1) + AK4558_CAD0)
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// datasheet page 81:
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// This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W).
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// The most significant five bits of the slave address are fixed as “00100”. The next bits are
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// CAD1 and CAD0 (device address bit). These bits identify the specific device on the bus.
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// The hard-wired input pins (CAD1 and CAD0) set these device address bits (Figure 69)
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// Power Management register
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#define AK4558_PWR_MNGT 0x00
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// D4 D3 D2 D1 D0
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// PMADR PMADL PMDAR PMDAL RSTN
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#define AK4558_PMADR (1u<<4)
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#define AK4558_PMADL (1u<<3)
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// PMADL/R: ADC L/Rch Power Management
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// 0: ADC L/Rch Power Down (default)
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// 1: Normal Operation
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#define AK4558_PMDAR (1u<<2)
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#define AK4558_PMDAL (1u<<1)
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// PMDAL/R: DAC L/Rch Power Management
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// 0: DAC L/Rch Power Down (default)
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// 1: Normal Operation
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#define AK4558_RSTN (1u)
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// RSTN: Internal Timing Reset
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// 0: Reset Register values are not reset.
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// 1: Normal Operation (default)
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// PLL Control register
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#define AK4558_PLL_CTRL 0X01
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// D4 D3 D2 D1 D0
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// PLL3 PLL2 PLL1 PLL0 PMPLL
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#define AK4558_PLL3 (1u<<4)
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#define AK4558_PLL2 (1u<<3)
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#define AK4558_PLL1 (1u<<2)
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#define AK4558_PLL0 (1u<<1)
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// PLL3-0: PLL Reference Clock Select (Table 16)
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// Default: “0010” (BICK pin=64fs)
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#define AK4558_PMPLL (1u)
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// PMPLL: PLL Power Management
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// 0: EXT Mode and Power down (default)
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// 1: PLL Mode and Power up
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// DAC TDM register
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#define AK4558_DAC_TDM 0X02
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// D1 D0
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// SDS1 SDS0
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#define AK4558_SDS1 (1u<<1)
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#define AK4558_SDS0 (1u)
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// SDS1-0: DAC TDM Data Select (Table 24)
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// Default: “00”
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// Control 1 register
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#define AK4558_CTRL_1 0X03
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// D7 D6 D5 D4 D3 D2 D1 D0
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// TDM1 TDM0 DIF2 DIF1 DIF0 ATS1 ATS0 SMUTE
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#define AK4558_TDM1 (1u<<7)
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#define AK4558_TDM0 (1u<<6)
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// TDM1-0: TDM Format Select (Table 23, Table 25, Table 26)
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// Default: “00” (Stereo Mode)
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#define AK4558_DIF2 (1u<<5)
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#define AK4558_DIF1 (1u<<4)
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#define AK4558_DIF0 (1u<<3)
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// DIF2-0: Audio Interface Format Mode Select (Table 23)
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// Default: “111” (32bit I2S)
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#define AK4558_ATS1 (1u<<2)
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#define AK4558_ATS0 (1u<<1)
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// ATS1-0: Transition Time Setting of Digital Attenuator (Table 31)
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// Default: “00”
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#define AK4558_SMUTE (1u)
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// SMUTE: Soft Mute Enable
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// 0: Normal Operation (default)
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// 1: All DAC outputs are soft muted.
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// Control 2 register
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#define AK4558_CTRL_2 0X04
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// D4 D3 D2 D1 D0
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// MCKS1 MCKS0 DFS1 DFS0 ACKS
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#define AK4558_MCKS1 (1u<<4)
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#define AK4558_MCKS0 (1u<<3)
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// MCKS1-0: Master Clock Input Frequency Select (Table 9, follows):
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// MCKS1 MCKS0 NSM DSM QSM
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// 0 0 256fs 256fs 128fs
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// 0 1 384fs 256fs 128fs
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// 1 0 512fs 256fs 128fs (default)
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// 1 1 768fs 256fs 128fs
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#define AK4558_DFS1 (1u<<2)
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#define AK4558_DFS0 (1u<<1)
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// DFS1-0: Sampling Speed Control (Table 8)
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// The setting of DFS1-0 bits is ignored when ACKS bit =“1”.
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#define AK4558_ACKS (1u)
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// ACKS: Automatic Clock Recognition Mode
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// 0: Disable, Manual Setting Mode (default)
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// 1: Enable, Auto Setting Mode
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// When ACKS bit = “1”, master clock frequency is detected automatically. In this case, the setting of
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// DFS1-0 bits is ignored. When ACKS bit = “0”, DFS1-0 bits set the sampling speed mode. The MCKI
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// frequency of each mode is detected automatically.
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// Mode Control register
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#define AK4558_MODE_CTRL 0X05
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// D6 D5 D4 D3 D2 D1 D0
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// FS3 FS2 FS1 FS0 BCKO1 BCKO0 LOPS
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#define AK4558_FS3 (1u<<6)
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#define AK4558_FS2 (1u<<5)
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#define AK4558_FS1 (1u<<4)
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#define AK4558_FS0 (1u<<3)
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// FS3-0: Sampling Frequency (Table 17, Table 18)
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// Default: “0101”
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#define AK4558_BCKO1 (1u<<2)
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#define AK4558_BCKO0 (1u<<1)
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// BCKO1-0: BICK Output Frequency Setting in Master Mode (Table 21)
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// Default: “01” (64fs)
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#define AK4558_LOPS (1u<<0)
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// LOPS: Power-save Mode of LOUT/ROUT
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// 0: Normal Operation (default)
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// 1: Power-save Mode
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// Filter Setting register
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#define AK4558_FLTR_SET 0x06
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// D7 D6 D5 D4 D3 D2 D1 D0
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// FIRDA2 FIRDA1 FIRDA0 SLDA SDDA SSLOW DEM1 DEM0
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#define AK4558_FIRDA2 (1u<<7)
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#define AK4558_FIRDA1 (1u<<6)
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#define AK4558_FIRDA0 (1u<<5)
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// FIRDA2-0: Out band noise eliminating Filters Setting (Table 32)
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// default: “001” (48kHz)
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#define AK4558_SLDA (1u<<4)
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// SLDA: DAC Slow Roll-off Filter Enable (Table 28)
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// 0: Sharp Roll-off filter (default)
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// 1: Slow Roll-off Filter
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#define AK4558_SDDA (1u<<3)
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// SDDA: DAC Short delay Filter Enable (Table 28)
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// 0: Normal filter
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// 1: Short delay Filter (default)
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#define AK4558_SSLOW (1u<<2)
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// SSLOW: Digital Filter Bypass Mode Enable
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// 0: Roll-off filter (default)
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// 1: Super Slow Roll-off Mode
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#define AK4558_DEM1 (1u<<1)
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#define AK4558_DEM0 (1u)
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// DEM1-0: De-emphasis response control for DAC (Table 22)
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// Default: “01”, OFF
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// HPF Enable, Filter Setting
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#define AK4558_HPF_EN_FLTR_SET 0x07
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// D3 D2 D1 D0
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// SLAD SDAD HPFER HPFEL
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#define AK4558_SLAD (1u<<3)
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// SLAD: ADC Slow Roll-off Filter Enable (Table 27)
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// 0: Sharp Roll-off filter (default)
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// 1: Slow Roll-off Filter
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#define AK4558_SDAD (1u<<2)
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// SDAD: ADC Short delay Filter Enable (Table 27)
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// 0: Normal filter
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// 1: Short delay Filter (default)
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#define AK4558_HPFER (1u<<1)
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#define AK4558_HPFEL (1u)
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// HPFEL/R: ADC HPF L/Rch Setting
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// 0: HPF L/Rch OFF
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// 1: HPF L/Rch ON (default)
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// LOUT Volume Control register
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#define AK4558_LOUT_VOL 0X08
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// D7 D6 D5 D4 D3 D2 D1 D0
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// ATL7 ATL6 ATL5 ATL4 ATL3 ATL2 ATL1 ATL0
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//
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// ATL 7-0: Attenuation Level (Table 30)
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// Default:FF(0dB)
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// ROUT Volume Control register
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#define AK4558_ROUT_VOL 0X09
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// D7 D6 D5 D4 D3 D2 D1 D0
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// ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0
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//
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// ATR 7-0: Attenuation Level (Table 30)
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// Default:FF(0dB)
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class AudioControlAK4558 : public AudioControl
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{
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public:
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bool enable(void); //enables the CODEC, does not power up ADC nor DAC (use enableIn() and enableOut() for selective power up)
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bool enableIn(void); //powers up ADC
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bool enableOut(void); //powers up DAC
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bool disable(void) { return (disableIn()&&disableOut()); } //powers down ADC/DAC
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bool disableIn(void); //powers down ADC
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bool disableOut(void); //powers down DAC
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bool volume(float n); //sets LOUT/ROUT volume to n (range 0.0 - 1.0)
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bool volumeLeft(float n); //sets LOUT volume to n (range 0.0 - 1.0)
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bool volumeRight(float n); //sets ROUT volume to n (range 0.0 - 1.0)
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bool inputLevel(float n) { return false; } //not supported by AK4558
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bool inputSelect(int n) { return false; } //sets inputs to mono left, mono right, stereo (default stereo), not yet implemented
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private:
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uint8_t registers[10];
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void initConfig(void);
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void readConfig(void);
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bool write(unsigned int reg, unsigned int val);
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uint8_t convertVolume(float vol);
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};
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#endif |