1024 lines
35 KiB
C++
1024 lines
35 KiB
C++
/* Audio Library for Teensy 3.X
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* Copyright (c) 2014, Paul Stoffregen, paul@pjrc.com
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*
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* Development of this audio library was funded by PJRC.COM, LLC by sales of
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* Teensy and Audio Adaptor boards. Please support PJRC's efforts to develop
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* open source software by purchasing Teensy or other PJRC products.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice, development funding notice, and this permission
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* notice shall be included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <Arduino.h>
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#include "control_sgtl5000.h"
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#include "Wire.h"
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#define CHIP_ID 0x0000
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// 15:8 PARTID 0xA0 - 8 bit identifier for SGTL5000
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// 7:0 REVID 0x00 - revision number for SGTL5000.
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#define CHIP_DIG_POWER 0x0002
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// 6 ADC_POWERUP 1=Enable, 0=disable the ADC block, both digital & analog,
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// 5 DAC_POWERUP 1=Enable, 0=disable the DAC block, both analog and digital
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// 4 DAP_POWERUP 1=Enable, 0=disable the DAP block
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// 1 I2S_OUT_POWERUP 1=Enable, 0=disable the I2S data output
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// 0 I2S_IN_POWERUP 1=Enable, 0=disable the I2S data input
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#define CHIP_CLK_CTRL 0x0004
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// 5:4 RATE_MODE Sets the sample rate mode. MCLK_FREQ is still specified
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// relative to the rate in SYS_FS
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// 0x0 = SYS_FS specifies the rate
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// 0x1 = Rate is 1/2 of the SYS_FS rate
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// 0x2 = Rate is 1/4 of the SYS_FS rate
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// 0x3 = Rate is 1/6 of the SYS_FS rate
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// 3:2 SYS_FS Sets the internal system sample rate (default=2)
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// 0x0 = 32 kHz
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// 0x1 = 44.1 kHz
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// 0x2 = 48 kHz
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// 0x3 = 96 kHz
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// 1:0 MCLK_FREQ Identifies incoming SYS_MCLK frequency and if the PLL should be used
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// 0x0 = 256*Fs
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// 0x1 = 384*Fs
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// 0x2 = 512*Fs
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// 0x3 = Use PLL
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// The 0x3 (Use PLL) setting must be used if the SYS_MCLK is not
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// a standard multiple of Fs (256, 384, or 512). This setting can
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// also be used if SYS_MCLK is a standard multiple of Fs.
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// Before this field is set to 0x3 (Use PLL), the PLL must be
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// powered up by setting CHIP_ANA_POWER->PLL_POWERUP and
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// CHIP_ANA_POWER->VCOAMP_POWERUP. Also, the PLL dividers must
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// be calculated based on the external MCLK rate and
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// CHIP_PLL_CTRL register must be set (see CHIP_PLL_CTRL register
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// description details on how to calculate the divisors).
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#define CHIP_I2S_CTRL 0x0006
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// 8 SCLKFREQ Sets frequency of I2S_SCLK when in master mode (MS=1). When in slave
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// mode (MS=0), this field must be set appropriately to match SCLK input
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// rate.
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// 0x0 = 64Fs
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// 0x1 = 32Fs - Not supported for RJ mode (I2S_MODE = 1)
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// 7 MS Configures master or slave of I2S_LRCLK and I2S_SCLK.
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// 0x0 = Slave: I2S_LRCLK an I2S_SCLK are inputs
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// 0x1 = Master: I2S_LRCLK and I2S_SCLK are outputs
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// NOTE: If the PLL is used (CHIP_CLK_CTRL->MCLK_FREQ==0x3),
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// the SGTL5000 must be a master of the I2S port (MS==1)
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// 6 SCLK_INV Sets the edge that data (input and output) is clocked in on for I2S_SCLK
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// 0x0 = data is valid on rising edge of I2S_SCLK
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// 0x1 = data is valid on falling edge of I2S_SCLK
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// 5:4 DLEN I2S data length (default=1)
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// 0x0 = 32 bits (only valid when SCLKFREQ=0),
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// not valid for Right Justified Mode
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// 0x1 = 24 bits (only valid when SCLKFREQ=0)
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// 0x2 = 20 bits
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// 0x3 = 16 bits
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// 3:2 I2S_MODE Sets the mode for the I2S port
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// 0x0 = I2S mode or Left Justified (Use LRALIGN to select)
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// 0x1 = Right Justified Mode
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// 0x2 = PCM Format A/B
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// 0x3 = RESERVED
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// 1 LRALIGN I2S_LRCLK Alignment to data word. Not used for Right Justified mode
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// 0x0 = Data word starts 1 I2S_SCLK delay after I2S_LRCLK
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// transition (I2S format, PCM format A)
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// 0x1 = Data word starts after I2S_LRCLK transition (left
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// justified format, PCM format B)
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// 0 LRPOL I2S_LRCLK Polarity when data is presented.
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// 0x0 = I2S_LRCLK = 0 - Left, 1 - Right
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// 1x0 = I2S_LRCLK = 0 - Right, 1 - Left
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// The left subframe should be presented first regardless of
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// the setting of LRPOL.
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#define CHIP_SSS_CTRL 0x000A
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// 14 DAP_MIX_LRSWAP DAP Mixer Input Swap
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// 0x0 = Normal Operation
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// 0x1 = Left and Right channels for the DAP MIXER Input are swapped.
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// 13 DAP_LRSWAP DAP Mixer Input Swap
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// 0x0 = Normal Operation
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// 0x1 = Left and Right channels for the DAP Input are swapped
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// 12 DAC_LRSWAP DAC Input Swap
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// 0x0 = Normal Operation
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// 0x1 = Left and Right channels for the DAC are swapped
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// 10 I2S_LRSWAP I2S_DOUT Swap
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// 0x0 = Normal Operation
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// 0x1 = Left and Right channels for the I2S_DOUT are swapped
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// 9:8 DAP_MIX_SELECT Select data source for DAP mixer
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// 0x0 = ADC
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// 0x1 = I2S_IN
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// 0x2 = Reserved
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// 0x3 = Reserved
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// 7:6 DAP_SELECT Select data source for DAP
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// 0x0 = ADC
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// 0x1 = I2S_IN
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// 0x2 = Reserved
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// 0x3 = Reserved
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// 5:4 DAC_SELECT Select data source for DAC (default=1)
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// 0x0 = ADC
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// 0x1 = I2S_IN
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// 0x2 = Reserved
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// 0x3 = DAP
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// 1:0 I2S_SELECT Select data source for I2S_DOUT
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// 0x0 = ADC
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// 0x1 = I2S_IN
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// 0x2 = Reserved
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// 0x3 = DAP
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#define CHIP_ADCDAC_CTRL 0x000E
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// 13 VOL_BUSY_DAC_RIGHT Volume Busy DAC Right
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// 0x0 = Ready
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// 0x1 = Busy - This indicates the channel has not reached its
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// programmed volume/mute level
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// 12 VOL_BUSY_DAC_LEFT Volume Busy DAC Left
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// 0x0 = Ready
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// 0x1 = Busy - This indicates the channel has not reached its
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// programmed volume/mute level
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// 9 VOL_RAMP_EN Volume Ramp Enable (default=1)
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// 0x0 = Disables volume ramp. New volume settings take immediate
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// effect without a ramp
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// 0x1 = Enables volume ramp
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// This field affects DAC_VOL. The volume ramp effects both
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// volume settings and mute When set to 1 a soft mute is enabled.
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// 8 VOL_EXPO_RAMP Exponential Volume Ramp Enable
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// 0x0 = Linear ramp over top 4 volume octaves
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// 0x1 = Exponential ramp over full volume range
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// This bit only takes effect if VOL_RAMP_EN is 1.
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// 3 DAC_MUTE_RIGHT DAC Right Mute (default=1)
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// 0x0 = Unmute
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// 0x1 = Muted
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// If VOL_RAMP_EN = 1, this is a soft mute.
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// 2 DAC_MUTE_LEFT DAC Left Mute (default=1)
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// 0x0 = Unmute
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// 0x1 = Muted
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// If VOL_RAMP_EN = 1, this is a soft mute.
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// 1 ADC_HPF_FREEZE ADC High Pass Filter Freeze
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// 0x0 = Normal operation
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// 0x1 = Freeze the ADC high-pass filter offset register. The
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// offset continues to be subtracted from the ADC data stream.
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// 0 ADC_HPF_BYPASS ADC High Pass Filter Bypass
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// 0x0 = Normal operation
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// 0x1 = Bypassed and offset not updated
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#define CHIP_DAC_VOL 0x0010
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// 15:8 DAC_VOL_RIGHT DAC Right Channel Volume. Set the Right channel DAC volume
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// with 0.5017 dB steps from 0 to -90 dB
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// 0x3B and less = Reserved
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// 0x3C = 0 dB
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// 0x3D = -0.5 dB
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// 0xF0 = -90 dB
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// 0xFC and greater = Muted
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// If VOL_RAMP_EN = 1, there is an automatic ramp to the
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// new volume setting.
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// 7:0 DAC_VOL_LEFT DAC Left Channel Volume. Set the Left channel DAC volume
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// with 0.5017 dB steps from 0 to -90 dB
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// 0x3B and less = Reserved
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// 0x3C = 0 dB
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// 0x3D = -0.5 dB
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// 0xF0 = -90 dB
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// 0xFC and greater = Muted
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// If VOL_RAMP_EN = 1, there is an automatic ramp to the
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// new volume setting.
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#define CHIP_PAD_STRENGTH 0x0014
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// 9:8 I2S_LRCLK I2S LRCLK Pad Drive Strength (default=1)
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// Sets drive strength for output pads per the table below.
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// VDDIO 1.8 V 2.5 V 3.3 V
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// 0x0 = Disable
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// 0x1 = 1.66 mA 2.87 mA 4.02 mA
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// 0x2 = 3.33 mA 5.74 mA 8.03 mA
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// 0x3 = 4.99 mA 8.61 mA 12.05 mA
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// 7:6 I2S_SCLK I2S SCLK Pad Drive Strength (default=1)
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// 5:4 I2S_DOUT I2S DOUT Pad Drive Strength (default=1)
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// 3:2 CTRL_DATA I2C DATA Pad Drive Strength (default=3)
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// 1:0 CTRL_CLK I2C CLK Pad Drive Strength (default=3)
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// (all use same table as I2S_LRCLK)
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#define CHIP_ANA_ADC_CTRL 0x0020
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// 8 ADC_VOL_M6DB ADC Volume Range Reduction
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// This bit shifts both right and left analog ADC volume
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// range down by 6.0 dB.
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// 0x0 = No change in ADC range
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// 0x1 = ADC range reduced by 6.0 dB
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// 7:4 ADC_VOL_RIGHT ADC Right Channel Volume
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// Right channel analog ADC volume control in 1.5 dB steps.
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// 0x0 = 0 dB
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// 0x1 = +1.5 dB
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// ...
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// 0xF = +22.5 dB
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// This range is -6.0 dB to +16.5 dB if ADC_VOL_M6DB is set to 1.
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// 3:0 ADC_VOL_LEFT ADC Left Channel Volume
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// (same scale as ADC_VOL_RIGHT)
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#define CHIP_ANA_HP_CTRL 0x0022
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// 14:8 HP_VOL_RIGHT Headphone Right Channel Volume (default 0x18)
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// Right channel headphone volume control with 0.5 dB steps.
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// 0x00 = +12 dB
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// 0x01 = +11.5 dB
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// 0x18 = 0 dB
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// ...
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// 0x7F = -51.5 dB
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// 6:0 HP_VOL_LEFT Headphone Left Channel Volume (default 0x18)
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// (same scale as HP_VOL_RIGHT)
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#define CHIP_ANA_CTRL 0x0024
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// 8 MUTE_LO LINEOUT Mute, 0 = Unmute, 1 = Mute (default 1)
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// 6 SELECT_HP Select the headphone input, 0 = DAC, 1 = LINEIN
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// 5 EN_ZCD_HP Enable the headphone zero cross detector (ZCD)
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// 0x0 = HP ZCD disabled
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// 0x1 = HP ZCD enabled
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// 4 MUTE_HP Mute the headphone outputs, 0 = Unmute, 1 = Mute (default)
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// 2 SELECT_ADC Select the ADC input, 0 = Microphone, 1 = LINEIN
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// 1 EN_ZCD_ADC Enable the ADC analog zero cross detector (ZCD)
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// 0x0 = ADC ZCD disabled
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// 0x1 = ADC ZCD enabled
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// 0 MUTE_ADC Mute the ADC analog volume, 0 = Unmute, 1 = Mute (default)
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#define CHIP_LINREG_CTRL 0x0026
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// 6 VDDC_MAN_ASSN Determines chargepump source when VDDC_ASSN_OVRD is set.
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// 0x0 = VDDA
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// 0x1 = VDDIO
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// 5 VDDC_ASSN_OVRD Charge pump Source Assignment Override
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// 0x0 = Charge pump source is automatically assigned based
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// on higher of VDDA and VDDIO
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// 0x1 = the source of charge pump is manually assigned by
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// VDDC_MAN_ASSN If VDDIO and VDDA are both the same
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// and greater than 3.1 V, VDDC_ASSN_OVRD and
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// VDDC_MAN_ASSN should be used to manually assign
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// VDDIO as the source for charge pump.
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// 3:0 D_PROGRAMMING Sets the VDDD linear regulator output voltage in 50 mV steps.
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// Must clear the LINREG_SIMPLE_POWERUP and STARTUP_POWERUP bits
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// in the 0x0030 (CHIP_ANA_POWER) register after power-up, for
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// this setting to produce the proper VDDD voltage.
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// 0x0 = 1.60
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// 0xF = 0.85
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#define CHIP_REF_CTRL 0x0028 // bandgap reference bias voltage and currents
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// 8:4 VAG_VAL Analog Ground Voltage Control
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// These bits control the analog ground voltage in 25 mV steps.
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// This should usually be set to VDDA/2 or lower for best
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// performance (maximum output swing at minimum THD). This VAG
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// reference is also used for the DAC and ADC voltage reference.
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// So changing this voltage scales the output swing of the DAC
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// and the output signal of the ADC.
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// 0x00 = 0.800 V
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// 0x1F = 1.575 V
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// 3:1 BIAS_CTRL Bias control
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// These bits adjust the bias currents for all of the analog
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// blocks. By lowering the bias current a lower quiescent power
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// is achieved. It should be noted that this mode can affect
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// performance by 3-4 dB.
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// 0x0 = Nominal
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// 0x1-0x3=+12.5%
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// 0x4=-12.5%
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// 0x5=-25%
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// 0x6=-37.5%
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// 0x7=-50%
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// 0 SMALL_POP VAG Ramp Control
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// Setting this bit slows down the VAG ramp from ~200 to ~400 ms
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// to reduce the startup pop, but increases the turn on/off time.
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// 0x0 = Normal VAG ramp
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// 0x1 = Slow down VAG ramp
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#define CHIP_MIC_CTRL 0x002A // microphone gain & internal microphone bias
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// 9:8 BIAS_RESISTOR MIC Bias Output Impedance Adjustment
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// Controls an adjustable output impedance for the microphone bias.
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// If this is set to zero the micbias block is powered off and
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// the output is highZ.
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// 0x0 = Powered off
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// 0x1 = 2.0 kohm
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// 0x2 = 4.0 kohm
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// 0x3 = 8.0 kohm
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// 6:4 BIAS_VOLT MIC Bias Voltage Adjustment
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// Controls an adjustable bias voltage for the microphone bias
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// amp in 250 mV steps. This bias voltage setting should be no
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// more than VDDA-200 mV for adequate power supply rejection.
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// 0x0 = 1.25 V
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// ...
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// 0x7 = 3.00 V
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// 1:0 GAIN MIC Amplifier Gain
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// Sets the microphone amplifier gain. At 0 dB setting the THD
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// can be slightly higher than other paths- typically around
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// ~65 dB. At other gain settings the THD are better.
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// 0x0 = 0 dB
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// 0x1 = +20 dB
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// 0x2 = +30 dB
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// 0x3 = +40 dB
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#define CHIP_LINE_OUT_CTRL 0x002C
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// 11:8 OUT_CURRENT Controls the output bias current for the LINEOUT amplifiers. The
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// nominal recommended setting for a 10 kohm load with 1.0 nF load cap
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// is 0x3. There are only 5 valid settings.
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// 0x0=0.18 mA
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// 0x1=0.27 mA
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// 0x3=0.36 mA
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// 0x7=0.45 mA
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// 0xF=0.54 mA
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// 5:0 LO_VAGCNTRL LINEOUT Amplifier Analog Ground Voltage
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// Controls the analog ground voltage for the LINEOUT amplifiers
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// in 25 mV steps. This should usually be set to VDDIO/2.
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// 0x00 = 0.800 V
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// ...
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// 0x1F = 1.575 V
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// ...
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// 0x23 = 1.675 V
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// 0x24-0x3F are invalid
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#define CHIP_LINE_OUT_VOL 0x002E
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// 12:8 LO_VOL_RIGHT LINEOUT Right Channel Volume (default=4)
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// Controls the right channel LINEOUT volume in 0.5 dB steps.
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// Higher codes have more attenuation.
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// 4:0 LO_VOL_LEFT LINEOUT Left Channel Output Level (default=4)
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// Used to normalize the output level of the left line output
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// to full scale based on the values used to set
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// LINE_OUT_CTRL->LO_VAGCNTRL and CHIP_REF_CTRL->VAG_VAL.
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// In general this field should be set to:
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// 40*log((VAG_VAL)/(LO_VAGCNTRL)) + 15
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// Suggested values based on typical VDDIO and VDDA voltages.
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// VDDA VAG_VAL VDDIO LO_VAGCNTRL LO_VOL_*
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// 1.8 V 0.9 3.3 V 1.55 0x06
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// 1.8 V 0.9 1.8 V 0.9 0x0F
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// 3.3 V 1.55 1.8 V 0.9 0x19
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// 3.3 V 1.55 3.3 V 1.55 0x0F
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// After setting to the nominal voltage, this field can be used
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// to adjust the output level in +/-0.5 dB increments by using
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// values higher or lower than the nominal setting.
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#define CHIP_ANA_POWER 0x0030 // power down controls for the analog blocks.
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// The only other power-down controls are BIAS_RESISTOR in the MIC_CTRL register
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// and the EN_ZCD control bits in ANA_CTRL.
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// 14 DAC_MONO While DAC_POWERUP is set, this allows the DAC to be put into left only
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// mono operation for power savings. 0=mono, 1=stereo (default)
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// 13 LINREG_SIMPLE_POWERUP Power up the simple (low power) digital supply regulator.
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// After reset, this bit can be cleared IF VDDD is driven
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// externally OR the primary digital linreg is enabled with
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// LINREG_D_POWERUP
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// 12 STARTUP_POWERUP Power up the circuitry needed during the power up ramp and reset.
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// After reset this bit can be cleared if VDDD is coming from
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// an external source.
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// 11 VDDC_CHRGPMP_POWERUP Power up the VDDC charge pump block. If neither VDDA or VDDIO
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// is 3.0 V or larger this bit should be cleared before analog
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// blocks are powered up.
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// 10 PLL_POWERUP PLL Power Up, 0 = Power down, 1 = Power up
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// When cleared, the PLL is turned off. This must be set before
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// CHIP_CLK_CTRL->MCLK_FREQ is programmed to 0x3. The
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// CHIP_PLL_CTRL register must be configured correctly before
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// setting this bit.
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// 9 LINREG_D_POWERUP Power up the primary VDDD linear regulator, 0 = Power down, 1 = Power up
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// 8 VCOAMP_POWERUP Power up the PLL VCO amplifier, 0 = Power down, 1 = Power up
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// 7 VAG_POWERUP Power up the VAG reference buffer.
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// Setting this bit starts the power up ramp for the headphone
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// and LINEOUT. The headphone (and/or LINEOUT) powerup should
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// be set BEFORE clearing this bit. When this bit is cleared
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// the power-down ramp is started. The headphone (and/or LINEOUT)
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// powerup should stay set until the VAG is fully ramped down
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// (200 to 400 ms after clearing this bit).
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// 0x0 = Power down, 0x1 = Power up
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// 6 ADC_MONO While ADC_POWERUP is set, this allows the ADC to be put into left only
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// mono operation for power savings. This mode is useful when
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// only using the microphone input.
|
|
// 0x0 = Mono (left only), 0x1 = Stereo
|
|
// 5 REFTOP_POWERUP Power up the reference bias currents
|
|
// 0x0 = Power down, 0x1 = Power up
|
|
// This bit can be cleared when the part is a sleep state
|
|
// to minimize analog power.
|
|
// 4 HEADPHONE_POWERUP Power up the headphone amplifiers
|
|
// 0x0 = Power down, 0x1 = Power up
|
|
// 3 DAC_POWERUP Power up the DACs
|
|
// 0x0 = Power down, 0x1 = Power up
|
|
// 2 CAPLESS_HEADPHONE_POWERUP Power up the capless headphone mode
|
|
// 0x0 = Power down, 0x1 = Power up
|
|
// 1 ADC_POWERUP Power up the ADCs
|
|
// 0x0 = Power down, 0x1 = Power up
|
|
// 0 LINEOUT_POWERUP Power up the LINEOUT amplifiers
|
|
// 0x0 = Power down, 0x1 = Power up
|
|
|
|
#define CHIP_PLL_CTRL 0x0032
|
|
// 15:11 INT_DIVISOR
|
|
// 10:0 FRAC_DIVISOR
|
|
|
|
#define CHIP_CLK_TOP_CTRL 0x0034
|
|
// 11 ENABLE_INT_OSC Setting this bit enables an internal oscillator to be used for the
|
|
// zero cross detectors, the short detect recovery, and the
|
|
// charge pump. This allows the I2S clock to be shut off while
|
|
// still operating an analog signal path. This bit can be kept
|
|
// on when the I2S clock is enabled, but the I2S clock is more
|
|
// accurate so it is preferred to clear this bit when I2S is present.
|
|
// 3 INPUT_FREQ_DIV2 SYS_MCLK divider before PLL input
|
|
// 0x0 = pass through
|
|
// 0x1 = SYS_MCLK is divided by 2 before entering PLL
|
|
// This must be set when the input clock is above 17 Mhz. This
|
|
// has no effect when the PLL is powered down.
|
|
|
|
#define CHIP_ANA_STATUS 0x0036
|
|
// 9 LRSHORT_STS This bit is high whenever a short is detected on the left or right
|
|
// channel headphone drivers.
|
|
// 8 CSHORT_STS This bit is high whenever a short is detected on the capless headphone
|
|
// common/center channel driver.
|
|
// 4 PLL_IS_LOCKED This bit goes high after the PLL is locked.
|
|
|
|
#define CHIP_ANA_TEST1 0x0038 // intended only for debug.
|
|
#define CHIP_ANA_TEST2 0x003A // intended only for debug.
|
|
|
|
#define CHIP_SHORT_CTRL 0x003C
|
|
// 14:12 LVLADJR Right channel headphone short detector in 25 mA steps.
|
|
// 0x3=25 mA
|
|
// 0x2=50 mA
|
|
// 0x1=75 mA
|
|
// 0x0=100 mA
|
|
// 0x4=125 mA
|
|
// 0x5=150 mA
|
|
// 0x6=175 mA
|
|
// 0x7=200 mA
|
|
// This trip point can vary by ~30% over process so leave plenty
|
|
// of guard band to avoid false trips. This short detect trip
|
|
// point is also effected by the bias current adjustments made
|
|
// by CHIP_REF_CTRL->BIAS_CTRL and by CHIP_ANA_TEST1->HP_IALL_ADJ.
|
|
// 10:8 LVLADJL Left channel headphone short detector in 25 mA steps.
|
|
// (same scale as LVLADJR)
|
|
// 6:4 LVLADJC Capless headphone center channel short detector in 50 mA steps.
|
|
// 0x3=50 mA
|
|
// 0x2=100 mA
|
|
// 0x1=150 mA
|
|
// 0x0=200 mA
|
|
// 0x4=250 mA
|
|
// 0x5=300 mA
|
|
// 0x6=350 mA
|
|
// 0x7=400 mA
|
|
// 3:2 MODE_LR Behavior of left/right short detection
|
|
// 0x0 = Disable short detector, reset short detect latch,
|
|
// software view non-latched short signal
|
|
// 0x1 = Enable short detector and reset the latch at timeout
|
|
// (every ~50 ms)
|
|
// 0x2 = This mode is not used/invalid
|
|
// 0x3 = Enable short detector with only manual reset (have
|
|
// to return to 0x0 to reset the latch)
|
|
// 1:0 MODE_CM Behavior of capless headphone central short detection
|
|
// (same settings as MODE_LR)
|
|
|
|
#define DAP_CONTROL 0x0100
|
|
#define DAP_PEQ 0x0102
|
|
#define DAP_BASS_ENHANCE 0x0104
|
|
#define DAP_BASS_ENHANCE_CTRL 0x0106
|
|
#define DAP_AUDIO_EQ 0x0108
|
|
#define DAP_SGTL_SURROUND 0x010A
|
|
#define DAP_FILTER_COEF_ACCESS 0x010C
|
|
#define DAP_COEF_WR_B0_MSB 0x010E
|
|
#define DAP_COEF_WR_B0_LSB 0x0110
|
|
#define DAP_AUDIO_EQ_BASS_BAND0 0x0116 // 115 Hz
|
|
#define DAP_AUDIO_EQ_BAND1 0x0118 // 330 Hz
|
|
#define DAP_AUDIO_EQ_BAND2 0x011A // 990 Hz
|
|
#define DAP_AUDIO_EQ_BAND3 0x011C // 3000 Hz
|
|
#define DAP_AUDIO_EQ_TREBLE_BAND4 0x011E // 9900 Hz
|
|
#define DAP_MAIN_CHAN 0x0120
|
|
#define DAP_MIX_CHAN 0x0122
|
|
#define DAP_AVC_CTRL 0x0124
|
|
#define DAP_AVC_THRESHOLD 0x0126
|
|
#define DAP_AVC_ATTACK 0x0128
|
|
#define DAP_AVC_DECAY 0x012A
|
|
#define DAP_COEF_WR_B1_MSB 0x012C
|
|
#define DAP_COEF_WR_B1_LSB 0x012E
|
|
#define DAP_COEF_WR_B2_MSB 0x0130
|
|
#define DAP_COEF_WR_B2_LSB 0x0132
|
|
#define DAP_COEF_WR_A1_MSB 0x0134
|
|
#define DAP_COEF_WR_A1_LSB 0x0136
|
|
#define DAP_COEF_WR_A2_MSB 0x0138
|
|
#define DAP_COEF_WR_A2_LSB 0x013A
|
|
|
|
#define SGTL5000_I2C_ADDR_CS_LOW 0x0A // CTRL_ADR0_CS pin low (normal configuration)
|
|
#define SGTL5000_I2C_ADDR_CS_HIGH 0x2A // CTRL_ADR0_CS pin high
|
|
|
|
|
|
void AudioControlSGTL5000::setAddress(uint8_t level)
|
|
{
|
|
if (level == LOW) {
|
|
i2c_addr = SGTL5000_I2C_ADDR_CS_LOW;
|
|
} else {
|
|
i2c_addr = SGTL5000_I2C_ADDR_CS_HIGH;
|
|
}
|
|
}
|
|
|
|
bool AudioControlSGTL5000::enable(void)
|
|
{
|
|
muted = true;
|
|
Wire.begin();
|
|
delay(5);
|
|
//Serial.print("chip ID = ");
|
|
//delay(5);
|
|
//unsigned int n = read(CHIP_ID);
|
|
//Serial.println(n, HEX);
|
|
|
|
write(CHIP_ANA_POWER, 0x4060); // VDDD is externally driven with 1.8V
|
|
write(CHIP_LINREG_CTRL, 0x006C); // VDDA & VDDIO both over 3.1V
|
|
write(CHIP_REF_CTRL, 0x01F2); // VAG=1.575, normal ramp, +12.5% bias current
|
|
write(CHIP_LINE_OUT_CTRL, 0x0F22); // LO_VAGCNTRL=1.65V, OUT_CURRENT=0.54mA
|
|
write(CHIP_SHORT_CTRL, 0x4446); // allow up to 125mA
|
|
write(CHIP_ANA_CTRL, 0x0137); // enable zero cross detectors
|
|
write(CHIP_ANA_POWER, 0x40FF); // power up: lineout, hp, adc, dac
|
|
write(CHIP_DIG_POWER, 0x0073); // power up all digital stuff
|
|
delay(400);
|
|
write(CHIP_LINE_OUT_VOL, 0x1D1D); // default approx 1.3 volts peak-to-peak
|
|
write(CHIP_CLK_CTRL, 0x0004); // 44.1 kHz, 256*Fs
|
|
write(CHIP_I2S_CTRL, 0x0130); // SCLK=32*Fs, 16bit, I2S format
|
|
// default signal routing is ok?
|
|
write(CHIP_SSS_CTRL, 0x0010); // ADC->I2S, I2S->DAC
|
|
write(CHIP_ADCDAC_CTRL, 0x0000); // disable dac mute
|
|
write(CHIP_DAC_VOL, 0x3C3C); // digital gain, 0dB
|
|
write(CHIP_ANA_HP_CTRL, 0x7F7F); // set volume (lowest level)
|
|
write(CHIP_ANA_CTRL, 0x0036); // enable zero cross detectors
|
|
//mute = false;
|
|
semi_automated = true;
|
|
return true;
|
|
}
|
|
|
|
unsigned int AudioControlSGTL5000::read(unsigned int reg)
|
|
{
|
|
unsigned int val;
|
|
Wire.beginTransmission(i2c_addr);
|
|
Wire.write(reg >> 8);
|
|
Wire.write(reg);
|
|
if (Wire.endTransmission(false) != 0) return 0;
|
|
if (Wire.requestFrom((int)i2c_addr, 2) < 2) return 0;
|
|
val = Wire.read() << 8;
|
|
val |= Wire.read();
|
|
return val;
|
|
}
|
|
|
|
bool AudioControlSGTL5000::write(unsigned int reg, unsigned int val)
|
|
{
|
|
if (reg == CHIP_ANA_CTRL) ana_ctrl = val;
|
|
Wire.beginTransmission(i2c_addr);
|
|
Wire.write(reg >> 8);
|
|
Wire.write(reg);
|
|
Wire.write(val >> 8);
|
|
Wire.write(val);
|
|
if (Wire.endTransmission() == 0) return true;
|
|
return false;
|
|
}
|
|
|
|
unsigned int AudioControlSGTL5000::modify(unsigned int reg, unsigned int val, unsigned int iMask)
|
|
{
|
|
unsigned int val1 = (read(reg)&(~iMask))|val;
|
|
if(!write(reg,val1)) return 0;
|
|
return val1;
|
|
}
|
|
|
|
bool AudioControlSGTL5000::volumeInteger(unsigned int n)
|
|
{
|
|
if (n == 0) {
|
|
muted = true;
|
|
write(CHIP_ANA_HP_CTRL, 0x7F7F);
|
|
return muteHeadphone();
|
|
} else if (n > 0x80) {
|
|
n = 0;
|
|
} else {
|
|
n = 0x80 - n;
|
|
}
|
|
if (muted) {
|
|
muted = false;
|
|
unmuteHeadphone();
|
|
}
|
|
n = n | (n << 8);
|
|
return write(CHIP_ANA_HP_CTRL, n); // set volume
|
|
}
|
|
|
|
bool AudioControlSGTL5000::volume(float left, float right)
|
|
{
|
|
unsigned short m=((0x7F-calcVol(right,0x7F))<<8)|(0x7F-calcVol(left,0x7F));
|
|
return write(CHIP_ANA_HP_CTRL, m);
|
|
}
|
|
|
|
bool AudioControlSGTL5000::micGain(unsigned int dB)
|
|
{
|
|
unsigned int preamp_gain, input_gain;
|
|
|
|
if (dB >= 40) {
|
|
preamp_gain = 3;
|
|
dB -= 40;
|
|
} else if (dB >= 30) {
|
|
preamp_gain = 2;
|
|
dB -= 30;
|
|
} else if (dB >= 20) {
|
|
preamp_gain = 1;
|
|
dB -= 20;
|
|
} else {
|
|
preamp_gain = 0;
|
|
}
|
|
input_gain = (dB * 2) / 3;
|
|
if (input_gain > 15) input_gain = 15;
|
|
|
|
return write(CHIP_MIC_CTRL, 0x0170 | preamp_gain)
|
|
&& write(CHIP_ANA_ADC_CTRL, (input_gain << 4) | input_gain);
|
|
}
|
|
|
|
// CHIP_ANA_ADC_CTRL
|
|
// Actual measured full-scale peak-to-peak sine wave input for max signal
|
|
// 0: 3.12 Volts p-p
|
|
// 1: 2.63 Volts p-p
|
|
// 2: 2.22 Volts p-p
|
|
// 3: 1.87 Volts p-p
|
|
// 4: 1.58 Volts p-p
|
|
// 5: 1.33 Volts p-p
|
|
// 6: 1.11 Volts p-p
|
|
// 7: 0.94 Volts p-p
|
|
// 8: 0.79 Volts p-p
|
|
// 9: 0.67 Volts p-p
|
|
// 10: 0.56 Volts p-p
|
|
// 11: 0.48 Volts p-p
|
|
// 12: 0.40 Volts p-p
|
|
// 13: 0.34 Volts p-p
|
|
// 14: 0.29 Volts p-p
|
|
// 15: 0.24 Volts p-p
|
|
bool AudioControlSGTL5000::lineInLevel(uint8_t left, uint8_t right)
|
|
{
|
|
if (left > 15) left = 15;
|
|
if (right > 15) right = 15;
|
|
return write(CHIP_ANA_ADC_CTRL, (left << 4) | right);
|
|
}
|
|
|
|
// CHIP_LINE_OUT_VOL
|
|
// Actual measured full-scale peak-to-peak sine wave output voltage:
|
|
// 0-12: output has clipping
|
|
// 13: 3.16 Volts p-p
|
|
// 14: 2.98 Volts p-p
|
|
// 15: 2.83 Volts p-p
|
|
// 16: 2.67 Volts p-p
|
|
// 17: 2.53 Volts p-p
|
|
// 18: 2.39 Volts p-p
|
|
// 19: 2.26 Volts p-p
|
|
// 20: 2.14 Volts p-p
|
|
// 21: 2.02 Volts p-p
|
|
// 22: 1.91 Volts p-p
|
|
// 23: 1.80 Volts p-p
|
|
// 24: 1.71 Volts p-p
|
|
// 25: 1.62 Volts p-p
|
|
// 26: 1.53 Volts p-p
|
|
// 27: 1.44 Volts p-p
|
|
// 28: 1.37 Volts p-p
|
|
// 29: 1.29 Volts p-p
|
|
// 30: 1.22 Volts p-p
|
|
// 31: 1.16 Volts p-p
|
|
unsigned short AudioControlSGTL5000::lineOutLevel(uint8_t n)
|
|
{
|
|
if (n > 31) n = 31;
|
|
else if (n < 13) n = 13;
|
|
return modify(CHIP_LINE_OUT_VOL,(n<<8)|n,(31<<8)|31);
|
|
}
|
|
|
|
unsigned short AudioControlSGTL5000::lineOutLevel(uint8_t left, uint8_t right)
|
|
{
|
|
if (left > 31) left = 31;
|
|
else if (left < 13) left = 13;
|
|
if (right > 31) right = 31;
|
|
else if (right < 13) right = 13;
|
|
return modify(CHIP_LINE_OUT_VOL,(right<<8)|left,(31<<8)|31);
|
|
}
|
|
|
|
unsigned short AudioControlSGTL5000::dacVolume(float n) // set both directly
|
|
{
|
|
if ((read(CHIP_ADCDAC_CTRL)&(3<<2)) != ((n>0 ? 0:3)<<2)) {
|
|
modify(CHIP_ADCDAC_CTRL,(n>0 ? 0:3)<<2,3<<2);
|
|
}
|
|
unsigned char m=calcVol(n,0xC0);
|
|
return modify(CHIP_DAC_VOL,((0xFC-m)<<8)|(0xFC-m),65535);
|
|
}
|
|
unsigned short AudioControlSGTL5000::dacVolume(float left, float right)
|
|
{
|
|
unsigned short adcdac=((right>0 ? 0:2)|(left>0 ? 0:1))<<2;
|
|
if ((read(CHIP_ADCDAC_CTRL)&(3<<2)) != adcdac) {
|
|
modify(CHIP_ADCDAC_CTRL,adcdac,1<<2);
|
|
}
|
|
unsigned short m=(0xFC-calcVol(right,0xC0))<<8|(0xFC-calcVol(left,0xC0));
|
|
return modify(CHIP_DAC_VOL,m,65535);
|
|
}
|
|
|
|
bool AudioControlSGTL5000::dacVolumeRamp()
|
|
{
|
|
return modify(CHIP_ADCDAC_CTRL, 0x300, 0x300);
|
|
}
|
|
|
|
bool AudioControlSGTL5000::dacVolumeRampLinear()
|
|
{
|
|
return modify(CHIP_ADCDAC_CTRL, 0x200, 0x300);
|
|
}
|
|
|
|
bool AudioControlSGTL5000::dacVolumeRampDisable()
|
|
{
|
|
return modify(CHIP_ADCDAC_CTRL, 0, 0x300);
|
|
}
|
|
|
|
|
|
|
|
|
|
unsigned short AudioControlSGTL5000::adcHighPassFilterEnable(void)
|
|
{
|
|
return modify(CHIP_ADCDAC_CTRL, 0, 3);
|
|
}
|
|
|
|
unsigned short AudioControlSGTL5000::adcHighPassFilterFreeze(void)
|
|
{
|
|
return modify(CHIP_ADCDAC_CTRL, 2, 3);
|
|
}
|
|
|
|
unsigned short AudioControlSGTL5000::adcHighPassFilterDisable(void)
|
|
{
|
|
return modify(CHIP_ADCDAC_CTRL, 1, 3);
|
|
}
|
|
|
|
|
|
// DAP_CONTROL
|
|
|
|
unsigned short AudioControlSGTL5000::audioPreProcessorEnable(void)
|
|
{
|
|
// audio processor used to pre-process analog input before Teensy
|
|
return write(DAP_CONTROL, 1) && write(CHIP_SSS_CTRL, 0x0013);
|
|
}
|
|
|
|
unsigned short AudioControlSGTL5000::audioPostProcessorEnable(void)
|
|
{
|
|
// audio processor used to post-process Teensy output before headphones/lineout
|
|
return write(DAP_CONTROL, 1) && write(CHIP_SSS_CTRL, 0x0070);
|
|
}
|
|
|
|
unsigned short AudioControlSGTL5000::audioProcessorDisable(void)
|
|
{
|
|
return write(CHIP_SSS_CTRL, 0x0010) && write(DAP_CONTROL, 0);
|
|
}
|
|
|
|
|
|
// DAP_PEQ
|
|
unsigned short AudioControlSGTL5000::eqFilterCount(uint8_t n) // valid to n&7, 0 thru 7 filters enabled.
|
|
{
|
|
return modify(DAP_PEQ,(n&7),7);
|
|
}
|
|
|
|
// DAP_AUDIO_EQ
|
|
unsigned short AudioControlSGTL5000::eqSelect(uint8_t n) // 0=NONE, 1=PEQ (7 IIR Biquad filters), 2=TONE (tone), 3=GEQ (5 band EQ)
|
|
{
|
|
return modify(DAP_AUDIO_EQ,n&3,3);
|
|
}
|
|
|
|
unsigned short AudioControlSGTL5000::eqBand(uint8_t bandNum, float n)
|
|
{
|
|
if(semi_automated) automate(1,3);
|
|
return dap_audio_eq_band(bandNum, n);
|
|
}
|
|
void AudioControlSGTL5000::eqBands(float bass, float mid_bass, float midrange, float mid_treble, float treble)
|
|
{
|
|
if(semi_automated) automate(1,3);
|
|
dap_audio_eq_band(0,bass);
|
|
dap_audio_eq_band(1,mid_bass);
|
|
dap_audio_eq_band(2,midrange);
|
|
dap_audio_eq_band(3,mid_treble);
|
|
dap_audio_eq_band(4,treble);
|
|
}
|
|
void AudioControlSGTL5000::eqBands(float bass, float treble) // dap_audio_eq(2);
|
|
{
|
|
if(semi_automated) automate(1,2);
|
|
dap_audio_eq_band(0,bass);
|
|
dap_audio_eq_band(4,treble);
|
|
}
|
|
|
|
// SGTL5000 PEQ Coefficient loader
|
|
void AudioControlSGTL5000::eqFilter(uint8_t filterNum, int *filterParameters)
|
|
{
|
|
// TODO: add the part that selects 7 PEQ filters.
|
|
if(semi_automated) automate(1,1,filterNum+1);
|
|
modify(DAP_FILTER_COEF_ACCESS,(uint16_t)filterNum,15);
|
|
write(DAP_COEF_WR_B0_MSB,(*filterParameters>>4)&65535);
|
|
write(DAP_COEF_WR_B0_LSB,(*filterParameters++)&15);
|
|
write(DAP_COEF_WR_B1_MSB,(*filterParameters>>4)&65535);
|
|
write(DAP_COEF_WR_B1_LSB,(*filterParameters++)&15);
|
|
write(DAP_COEF_WR_B2_MSB,(*filterParameters>>4)&65535);
|
|
write(DAP_COEF_WR_B2_LSB,(*filterParameters++)&15);
|
|
write(DAP_COEF_WR_A1_MSB,(*filterParameters>>4)&65535);
|
|
write(DAP_COEF_WR_A1_LSB,(*filterParameters++)&15);
|
|
write(DAP_COEF_WR_A2_MSB,(*filterParameters>>4)&65535);
|
|
write(DAP_COEF_WR_A2_LSB,(*filterParameters++)&15);
|
|
write(DAP_FILTER_COEF_ACCESS,(uint16_t)0x100|filterNum);
|
|
}
|
|
|
|
/* Valid values for dap_avc parameters
|
|
|
|
maxGain; Maximum gain that can be applied
|
|
0 - 0 dB
|
|
1 - 6.0 dB
|
|
2 - 12 dB
|
|
|
|
lbiResponse; Integrator Response
|
|
0 - 0 mS
|
|
1 - 25 mS
|
|
2 - 50 mS
|
|
3 - 100 mS
|
|
|
|
hardLimit
|
|
0 - Hard limit disabled. AVC Compressor/Expander enabled.
|
|
1 - Hard limit enabled. The signal is limited to the programmed threshold (signal saturates at the threshold)
|
|
|
|
threshold
|
|
floating point in range 0 to -96 dB
|
|
|
|
attack
|
|
floating point figure is dB/s rate at which gain is increased
|
|
|
|
decay
|
|
floating point figure is dB/s rate at which gain is reduced
|
|
*/
|
|
unsigned short AudioControlSGTL5000::autoVolumeControl(uint8_t maxGain, uint8_t lbiResponse, uint8_t hardLimit, float threshold, float attack, float decay)
|
|
{
|
|
//if(semi_automated&&(!read(DAP_CONTROL)&1)) audioProcessorEnable();
|
|
if(maxGain>2) maxGain=2;
|
|
lbiResponse&=3;
|
|
hardLimit&=1;
|
|
uint8_t thresh=(pow(10,threshold/20)*0.636)*pow(2,15);
|
|
uint8_t att=(1-pow(10,-(attack/(20*44100))))*pow(2,19);
|
|
uint8_t dec=(1-pow(10,-(decay/(20*44100))))*pow(2,23);
|
|
write(DAP_AVC_THRESHOLD,thresh);
|
|
write(DAP_AVC_ATTACK,att);
|
|
write(DAP_AVC_DECAY,dec);
|
|
return modify(DAP_AVC_CTRL,maxGain<<12|lbiResponse<<8|hardLimit<<5,3<<12|3<<8|1<<5);
|
|
}
|
|
unsigned short AudioControlSGTL5000::autoVolumeEnable(void)
|
|
{
|
|
return modify(DAP_AVC_CTRL, 1, 1);
|
|
}
|
|
unsigned short AudioControlSGTL5000::autoVolumeDisable(void)
|
|
{
|
|
return modify(DAP_AVC_CTRL, 0, 1);
|
|
}
|
|
|
|
unsigned short AudioControlSGTL5000::enhanceBass(float lr_lev, float bass_lev)
|
|
{
|
|
return modify(DAP_BASS_ENHANCE_CTRL,((0x3F-calcVol(lr_lev,0x3F))<<8) | (0x7F-calcVol(bass_lev,0x7F)), (0x3F<<8) | 0x7F);
|
|
}
|
|
unsigned short AudioControlSGTL5000::enhanceBass(float lr_lev, float bass_lev, uint8_t hpf_bypass, uint8_t cutoff)
|
|
{
|
|
modify(DAP_BASS_ENHANCE,(hpf_bypass&1)<<8|(cutoff&7)<<4,1<<8|7<<4);
|
|
return enhanceBass(lr_lev,bass_lev);
|
|
}
|
|
unsigned short AudioControlSGTL5000::enhanceBassEnable(void)
|
|
{
|
|
return modify(DAP_BASS_ENHANCE, 1, 1);
|
|
}
|
|
unsigned short AudioControlSGTL5000::enhanceBassDisable(void)
|
|
{
|
|
return modify(DAP_BASS_ENHANCE, 0, 1);
|
|
}
|
|
unsigned short AudioControlSGTL5000::surroundSound(uint8_t width)
|
|
{
|
|
return modify(DAP_SGTL_SURROUND,(width&7)<<4,7<<4);
|
|
}
|
|
unsigned short AudioControlSGTL5000::surroundSound(uint8_t width, uint8_t select)
|
|
{
|
|
return modify(DAP_SGTL_SURROUND,((width&7)<<4)|(select&3), (7<<4)|3);
|
|
}
|
|
unsigned short AudioControlSGTL5000::surroundSoundEnable(void)
|
|
{
|
|
return modify(DAP_SGTL_SURROUND, 3, 3);
|
|
}
|
|
unsigned short AudioControlSGTL5000::surroundSoundDisable(void)
|
|
{
|
|
return modify(DAP_SGTL_SURROUND, 0, 3);
|
|
}
|
|
|
|
unsigned char AudioControlSGTL5000::calcVol(float n, unsigned char range)
|
|
{
|
|
// n=(n*(((float)range)/100))+0.499;
|
|
n=(n*(float)range)+0.499;
|
|
if ((unsigned char)n>range) n=range;
|
|
return (unsigned char)n;
|
|
}
|
|
|
|
// DAP_AUDIO_EQ_BASS_BAND0 & DAP_AUDIO_EQ_BAND1 & DAP_AUDIO_EQ_BAND2 etc etc
|
|
unsigned short AudioControlSGTL5000::dap_audio_eq_band(uint8_t bandNum, float n) // by signed percentage -100/+100; dap_audio_eq(3);
|
|
{
|
|
n=(n*48)+0.499;
|
|
if(n<-47) n=-47;
|
|
if(n>48) n=48;
|
|
n+=47;
|
|
return modify(DAP_AUDIO_EQ_BASS_BAND0+(bandNum*2),(unsigned int)n,127);
|
|
}
|
|
|
|
void AudioControlSGTL5000::automate(uint8_t dap, uint8_t eq)
|
|
{
|
|
//if((dap!=0)&&(!(read(DAP_CONTROL)&1))) audioProcessorEnable();
|
|
if((read(DAP_AUDIO_EQ)&3) != eq) eqSelect(eq);
|
|
}
|
|
|
|
void AudioControlSGTL5000::automate(uint8_t dap, uint8_t eq, uint8_t filterCount)
|
|
{
|
|
automate(dap,eq);
|
|
if (filterCount > (read(DAP_PEQ)&7)) eqFilterCount(filterCount);
|
|
}
|
|
|
|
|
|
// if(SGTL5000_PEQ) quantization_unit=524288; if(AudioFilterBiquad) quantization_unit=2147483648;
|
|
void calcBiquad(uint8_t filtertype, float fC, float dB_Gain, float Q, uint32_t quantization_unit, uint32_t fS, int *coef)
|
|
{
|
|
|
|
// I used resources like http://www.musicdsp.org/files/Audio-EQ-Cookbook.txt
|
|
// to make this routine, I tested most of the filter types and they worked. Such filters have limits and
|
|
// before calling this routine with varying values the end user should check that those values are limited
|
|
// to valid results.
|
|
|
|
float A;
|
|
if(filtertype<FILTER_PARAEQ) A=pow(10,dB_Gain/20); else A=pow(10,dB_Gain/40);
|
|
float W0 = 2*3.14159265358979323846*fC/fS;
|
|
float cosw=cosf(W0);
|
|
float sinw=sinf(W0);
|
|
//float alpha = sinw*sinh((log(2)/2)*BW*W0/sinw);
|
|
//float beta = sqrt(2*A);
|
|
float alpha = sinw / (2 * Q);
|
|
float beta = sqrtf(A)/Q;
|
|
float b0,b1,b2,a0,a1,a2;
|
|
|
|
switch(filtertype) {
|
|
case FILTER_LOPASS:
|
|
b0 = (1.0F - cosw) * 0.5F; // =(1-COS($H$2))/2
|
|
b1 = 1.0F - cosw;
|
|
b2 = (1.0F - cosw) * 0.5F;
|
|
a0 = 1.0F + alpha;
|
|
a1 = 2.0F * cosw;
|
|
a2 = alpha - 1.0F;
|
|
break;
|
|
case FILTER_HIPASS:
|
|
b0 = (1.0F + cosw) * 0.5F;
|
|
b1 = -(cosw + 1.0F);
|
|
b2 = (1.0F + cosw) * 0.5F;
|
|
a0 = 1.0F + alpha;
|
|
a1 = 2.0F * cosw;
|
|
a2 = alpha - 1.0F;
|
|
break;
|
|
case FILTER_BANDPASS:
|
|
b0 = alpha;
|
|
b1 = 0.0F;
|
|
b2 = -alpha;
|
|
a0 = 1.0F + alpha;
|
|
a1 = 2.0F * cosw;
|
|
a2 = alpha - 1.0F;
|
|
break;
|
|
case FILTER_NOTCH:
|
|
b0=1;
|
|
b1=-2*cosw;
|
|
b2=1;
|
|
a0=1+alpha;
|
|
a1=2*cosw;
|
|
a2=-(1-alpha);
|
|
break;
|
|
case FILTER_PARAEQ:
|
|
b0 = 1 + (alpha*A);
|
|
b1 =-2 * cosw;
|
|
b2 = 1 - (alpha*A);
|
|
a0 = 1 + (alpha/A);
|
|
a1 = 2 * cosw;
|
|
a2 =-(1-(alpha/A));
|
|
break;
|
|
case FILTER_LOSHELF:
|
|
b0 = A * ((A+1.0F) - ((A-1.0F)*cosw) + (beta*sinw));
|
|
b1 = 2.0F * A * ((A-1.0F) - ((A+1.0F)*cosw));
|
|
b2 = A * ((A+1.0F) - ((A-1.0F)*cosw) - (beta*sinw));
|
|
a0 = (A+1.0F) + ((A-1.0F)*cosw) + (beta*sinw);
|
|
a1 = 2.0F * ((A-1.0F) + ((A+1.0F)*cosw));
|
|
a2 = -((A+1.0F) + ((A-1.0F)*cosw) - (beta*sinw));
|
|
break;
|
|
case FILTER_HISHELF:
|
|
b0 = A * ((A+1.0F) + ((A-1.0F)*cosw) + (beta*sinw));
|
|
b1 = -2.0F * A * ((A-1.0F) + ((A+1.0F)*cosw));
|
|
b2 = A * ((A+1.0F) + ((A-1.0F)*cosw) - (beta*sinw));
|
|
a0 = (A+1.0F) - ((A-1.0F)*cosw) + (beta*sinw);
|
|
a1 = -2.0F * ((A-1.0F) - ((A+1.0F)*cosw));
|
|
a2 = -((A+1.0F) - ((A-1.0F)*cosw) - (beta*sinw));
|
|
default:
|
|
b0 = 0.5;
|
|
b1 = 0.0;
|
|
b2 = 0.0;
|
|
a0 = 1.0;
|
|
a1 = 0.0;
|
|
a2 = 0.0;
|
|
}
|
|
|
|
a0=(a0*2)/(float)quantization_unit; // once here instead of five times there...
|
|
b0/=a0;
|
|
*coef++=(int)(b0+0.499);
|
|
b1/=a0;
|
|
*coef++=(int)(b1+0.499);
|
|
b2/=a0;
|
|
*coef++=(int)(b2+0.499);
|
|
a1/=a0;
|
|
*coef++=(int)(a1+0.499);
|
|
a2/=a0;
|
|
*coef++=(int)(a2+0.499);
|
|
}
|
|
|